As a basic semiconductor device, transistors are widely used. With increase of component density and integration degree of semiconductor devices, gate size of transistors becomes shorter than before. However, the shortened gate of transistors can generate a short channel effect in transistors, thus causing leakage current and ultimately affecting electrical performance of semiconductor devices. Currently, a conventional technology mainly focuses on improving stress of the channel region in a transistor to enhance carrier mobility, thereby increasing drive current of the transistor to reduce leakage current.
A conventional method of improving stress of the channel region in a transistor includes: forming a stress layer in the source/drain region of the transistor. In a PMOS transistor, the stress layer can be made of silicon germanium (SiGe), thus compressive stress is generated due to crystal lattice mismatch between silicon and silicon germanium, thereby improving performance of the PMOS transistor. In an NMOS transistor, the stress layer can be made of silicon carbide (SiC), thus tensile stress is generated due to crystal lattice mismatch between silicon and silicon carbide, thereby improving performance of the NMOS transistor.
FIGS. 1-3 show cross sectional views of a conventional transistor having a stress layer at various formation stages. As shown in FIGS. 1-3, the fabrication method includes: providing a semiconductor substrate 10 having a gate structure 11 on a top surface of the semiconductor substrate 10 and containing a well region in the semiconductor substrate 10 (FIG. 1); forming openings 12 in the semiconductor substrate 10 on both sides of the gate structure 11, the sidewalls of the openings 12 and the surface of the semiconductor substrate 10 being configured to be a “Σ” (Sigma) shape having a vertex extending to the bottom of the gate structure 11 (FIG. 2); and forming a stress layer 13 in the openings 12 by a selective epitaxial deposition process, the stress layer 13 being made of silicon germanium or silicon carbide.
According to the conductive type of a transistor, the stress layer 13 can be doped with P-type or N-type ions to form a source region and a drain region in the semiconductor substrate 10 on both sides of the gate structure to form a PMOS transistor and a NMOS transistor. Type of doped ions in the well region is opposite to the type of doped ions in the stress layer 13.
However, a transistor having a stress layer formed by a conventional method is still prone to leakage current or a short channel effect with undesirable performance.